5080 POL Application Notes
The 5080 series are radiation hardened, non-isolated, synchronous switching buck point of load (POL) regulators.
Non-isolated DC-DC converters are three terminal devices, having an input terminal, an output terminal and a common terminal.
Buck converters generate an output voltage that is lower than the input voltage.
In simplest form, the buck converter uses a FET, a diode and an inductor.
In order to obtain higher power efficiency, the rectifying diode in the non-isolated DC-DC converter is replaced with a second FET. The forward voltage drop of the diode is usually higher than the drop across the second FET, therefore power losses are lower. The FET must be switched in synchronism with the waveform that would appear across the diode. Therefore, DC-DC converters that use a second FET to perform the action of the diode are called synchronous rectification devices.
Simplified Block Diagram
The block diagram of the model 5080 shows that input power is applied to an upper power switch. The switch is driven at a 100 kHz rate by the pulse width modulator (PWM) circuit.
The switched waveform is then fed through the Buck choke.
A lower switch is connected in parallel with the output buck rectifier. The lower switch is connected between the upper switch output and ground.
The ripple filtered output passes through a common mode inductor to reduce output spike voltages. The external damping capacitor is supplied by the user to optimize load application and removal transients as well as to lower the output ripple.
The output voltage is passed through the output sense circuit, which permits voltage sensing directly at the 5080's output pins for best static load regulation.
Input pins are provided for external sync (this can also be used for phase staggering of multiple 5080's), an inhibit pin and a voltage adjust pin. Output pins include a 5 VDC voltage reference (for output voltage adjustment, a BIT analog output and a current telemetry output (useful in paralleling multiple converters).
Input Voltage Source:
The 5080 converters are intended to operate from an intermediate bus. This intermediate bus is a voltage of 11 to 16 VDC (with a preferred voltage of 12 VDC) that is supplied by another, front-end power converter. The front-end power converter developing the intermediate bus is exposed to the bus variations and transients. Also, it is expected that the front-end converter will accommodate the MIL-STD-461 type EMI filtering requirements of the system as applicable.
Although the 5080 converters do not contain full internal EMI filters, they do feature common mode filtering on input and output power lines. This provides a substantial reduction of voltage spikes.
A fully loaded 5080 module can draw up to 1000 mA ripple current at its switching frequency of 100 kHz. Therefore, any front end DC-DC converter should provide appropriate decoupling capacitance at its output terminals to supply this maximum ripple current. A minimum input decoupling capacitance of 30 microfarads (ceramic MLC or low ESR types) per 5080 module is recommended.
For most applications, an input voltage source that is nominally 12 VDC will provide the best electrical performance. A nominal 15 VDC source may also be used, however, the conversion efficiencies will be slightly lower.
Output Voltage:
There are nine 5080 models that produce a positive output voltage. Output voltage types and adjustment ranges are shown on the 5080 data sheet.
Output Current:
Output current of the 5080 units is limited to 4 amperes or to the current produced at 10 watts output (considering the nominal output voltage), whichever is lower. The maximum output current is constant current limited.
External Output Capacitance:
Due to the small size of the 5080, the internal output capacitance is limited in value to that necessary for high frequency filtering. For good load transient response, the 5080 data sheet shows a recommended minimum and maximum external capacitance that should be supplied by the user or present in the user's load. The use of low ESR types, such as multiple solid Tantalum chips in parallel is encouraged, as ripple voltage will also be reduced.
Output Voltage Temperature Coefficients
Voltage limits for Model 5080 parts shown in the MDI data sheets are the nominal 25°C values. At temperatures outside 25°C, the output voltage may vary ± 100PPM/°C maximum with base temperature.
Output Ripple
Due to its small size, the internal capacitance of the 5080 is limited. For good load removal and load application response, a minimum value of external capacitance is recommended.
When selecting external capacitors, low ESR solid tantalum capacitors are preferred. Capacitor leads with excessive series inductance should not be used, since this will add impedance and negate the benefit of the external capacitance. Relatively large amounts of external capacitance may be added, but do not exceed the data sheet guidelines without consulting MDI.
Four Terminal Capacitor Method for Improved Filtering
To reduce high frequency spikes, multilayer ceramic capacitors in surface mount chip form can be used. For best results, the capacitor should be connected as a four terminal device. An external series common mode inductor or ferrite beads can also be used between the converter and the capacitor.
Output Ripple Vs. Temperature
The fundamental output ripple of the 5080 converters is primarily dependent on the absolute capacitance value of the external output capacitors (when the output capacitors are multilayer ceramic types), or the ESR of the output capacitors (when the output capacitors are solid tantalum types). The selection of output capacitor depends on the output voltage and type of converter. However, the following effects occur at temperature. For units using ceramic output capacitors, the capacitance falls off sharply at high and low temperature extremes. Although the low ESR of ceramic capacitors results in very low ripple voltages, it is not unusual for ripple voltage to double at the high and low temperature extremes. For units using solid tantalum output capacitors, the ESR also rises sharply at low temperature extremes. Therefore, users should conservatively assume a ripple temperature coefficient of 1% per °C increase over the 25°C base numbers.
Short Circuit and Overload Protection
Model 5080 DC-DC converters contain constant current limiting for protection against inadvertent output short circuits and overloads. The current limiting set point is approximately 125% of rated output current.
Output Over Voltage Protection
Model 5080 DC-DC converters do not contain any internal over voltage protection circuitry. If this function is required, the user should implement it externally. Because the 5080 is non-isolated, in the extremely unlikely event of a failed shorted switching FET, the input voltage could appear at the output pins. If warranted, external OVP should be used.
Output Load Transient response
The output load removal and load application transient voltage is a function of the external capacitance and the magnitude of the current step. The following table lists the magnitude of the output voltage transient for a 25% to 75% rated load change, with the minimum recommended external capacitance.
Back Voltage
A back voltage may be applied to the output of the 5080 DC-DC Converter, whether it be energized or de-energized. Up to 20% above the output voltage rating may be safely applied.
| Nom.V out |
Ext C (min.), uF |
Zout (ohms) |
Delta V for 50% step |
Ext C (max.), uF |
Zout (ohms) |
Delta V for 50% step |
|---|---|---|---|---|---|---|
| 7.5 | 500 | 0.6146 | 0.4087 | 2000 | 0.3162 | 0.2103 |
| 5 | 500 | 0.302 | 0.302 | 2000 | 0.1577 | 0.1577 |
| 3.3 | 1000 | 0.2951 | 0.4426 | 4000 | 0.1119 | 0.1679 |
| 2.5 | 1000 | 0.1063 | 0.2127 | 4000 | 0.0557 | 0.1113 |
| 2 | 1000 | 0.1063 | 0.2127 | 4000 | 0.0557 | 0.1113 |
| 1.8 | 1000 | 0.1063 | 0.2127 | 4000 | 0.0557 | 0.1113 |
| 1.5 | 1000 | 0.1063 | 0.2127 | 4000 | 0.0557 | 0.1113 |
| 1.2 | 1000 | 0.1063 | 0.2127 | 4000 | 0.0557 | 0.1113 |
| 1 | 1000 | 0.1063 | 0.2127 | 4000 | 0.0557 | 0.1113 |
Pin Functions
- Pin 1 Positive Input Power
- Pin 2 Positive Input Power
- Pin 3 Positive Input Power
- Pin 4 Input/Output Com
- Pin 5 Input/Output Com
- Pin 6 Input/Output Com
- Pin 7 Output
- Pin 8 Output
- Pin 9 Output
- Pin 10 Case Ground
- Pin 11 Paralleling Input
- Pin 12 Paralleling Output
- Pin 13 V ref: A nominal +5 VDC reference used for output voltage trimming
- Pin 14 Adjust: Input pin used for voltage trimming and paralleling
- Pin 15 I out: Signal proportional to output current , used for paralleling
- Pin 16 Sync Input: Input pin used to accept external 100 kHz. sync signal
- Pin 17 Inhibit (Ground to inhibit) BIT: An analog output line indicating the module status
- Pin 18 Inhibit (Ground to inhibit) BIT: An analog output line indicating the module status
Voltage Reference (Pin 13)
The voltage reference pin is primarily used for downward voltage adjustment of the output. However, it may also be used for other applications. Up to 10 milliamperes may be drawn by the user. This current, if used, is ultimately drawn from the input voltage.
Output Voltage Adjustment (Pin 14)
The adjust pin function (pin 14) allows the user to set the 5080 output voltage slightly above or below it's initial set point. The recommended adjust range for each part type is listed in the data sheet.
When trimming for an increased output magnitude the adjust resistor is connected to the common ground. When trimming for a decreased output magnitude the adjust resistor is connected to the V ref pin (pin 13).
The adjust pin is connected to an internal 10K resistor, whose purpose is to prevent damage to the internal circuits and to reduce noise pickup.
The following table gives applicable resistor values for each 5080 type, as well as which equations to use to calculate the external adjust resistor value. For purposes of computing the external adjust resistor power dissipation, a maximum of 2.5 VDC appears across the external adjustment resistor.
If the external adjust feature is not used, both the adjust pin (14) and the V ref pin (13) should be left unconnected.
When the converter is adjusted upwards, the output power should be limited to 10 watts, or the output current should be limited to 4 amperes, whichever is less.
| Vout | R1 | R2 | R3 | Equation for Upward Adjust | Equation for Downward Adjust |
|---|---|---|---|---|---|
| 7.5 | 20K | 10K | 10K | Equations 1A and 3 | Equations 2A and 3 |
| 5 | 10K | 10K | 10K | Equations 1A and 3 | Equations 2A and 3 |
| 3.3 | 16K | 50K | 10K | Equations 1A and 3 | Equations 2A and 3 |
| 2.5 | 10K | Infinity | 10K | Equations 1A and 3 | Equations 2A and 3 |
| 2 | 10K | 50K | 10K | Equations 1B and 3 | Equations 2B and 3 |
| 1.8 | 10K | 35.7K | 10K | Equations 1B and 3 | Equations 2B and 3 |
| 1.5 | 10K | 25K | 10K | Equations 1B and 3 | Equations 2B and 3 |
| 1.2 | 10K | 19.23K | 10K | Equations 1B and 3 | Equations 2B and 3 |
| 1 | 10K | 16.67K | 10K | Equations 1B and 3 | Equations 2B and 3 |
Equation 1A
Equation 1B
Equation 2A
Equation 2B
Equation 3
Output Current (Pin 15)
An analog of the output current is provided in pin 15. This is useful in paralleling applications.
| Nom. Vout |
Vin=12 VDC |
Vin=15 VDC |
|---|---|---|
| 7.5 | 205 | 164 |
| 5 | 136 | 109 |
| 3.3 | 90 | 72 |
| 2.5 | 68 | 55 |
| 2 | 55 | 44 |
| 1.8 | 49 | 39 |
| 1.5 | 41 | 33 |
| 1.2 | 32 | 26 |
| 1 | 27 | 22 |
Connecting 5080 Units in parallel for higher output current
The outputs of like converters may be connected in parallel to support higher load current requirements. They will not, however, share the output load to any determinate extent without interconnecting the paralleling pins provided for the purpose.
5080 converters may be configured to share total current of higher current loads to within nominally ten percent by interconnecting the parallel in and parallel out pins. One of up to five 5080s should be selected as the "master" and the other 5080's as the "slave(s)". Connect the parallel out of the master to the parallel input of the slave(s). Paralleled units should be located physically close to each other to minimize wire drops.
In this scheme, external ballasting resistance and external circuitry can be avoided and very satisfactory load current sharing achieved.
Output "OR"ing diodes may be implemented if desired, and their volt drop compensated for by implementing the upward adjust function of output voltage
Sync Input (Pin 16)
Pin 16 is the Sync Input. The 5080 hybrid operates at approximately 95 kHz and may be synchronized to frequencies from 95 to 105 kHz. The sync input pulse should meet the following levels as shown in the diagram. The sync input should sit at nominal 5 VDC and transition to ground level at a 10% ± 1% duty cycle. It should be noted that the internal oscillator runs at the switching frequency. Other frequencies are also available on special order. Contact MDI's Sales and Marketing Department for other sync frequencies.
Synchronizing the power conversion units within an extremely sensitive system ensures that any noise generation is coincident with the system clock.
If two or more 5080 units are used, a phase staggered sync signal may be applied in order to reduce the overall input and output ripple.
The "sync pin" should be left open if unused.
Typical Sync Waveform
Inhibit/BIT (Pin 17,18)
Pins 17and 18 are the BIT/Inhibit pins. The BIT signal is an analog signal that is the buffered output of the internal PWM error amplifier. The source impedance of the BIT line is approximately 50K ohms.
The normal voltage range of the BIT line is 0.9 VDC to 3.3 VDC. A voltage lower or higher than these values indicates that the internal regulating loop considers the output voltage to be too high or too low, respectively.
The BIT line may be connected to an external comparator window detector to produce a discrete BIT signal.
Pins 17 and 18 are also the Inhibit pins. To inhibit the output voltage, the inhibit input should be returned to the common ground pins, within 0.5 VDC. When the inhibit pin is connected to the common ground, the inhibit current is approximately 1 milliampere.
An open collector transistor may be used to actuate the inhibit. However, the inhibit pins may be safely connected to any positive voltage up to 16 VDC. Therefore, the inhibit pins may also be safely driven by standard 3.3 or 5 VDC logic devices.
When not inhibited, pins 17 and 18 should either be floating or returned to a voltage higher than 3.3 VDC.
Inhibit Circuits
Preferred Circuit Interface for Inhibit
Efficiency of 5080 POL Converters
Dual FET synchronous rectification and non-isolated design afford very high operating efficiencies for the 5080 series POL converters. Even very low operating voltages of 1. 2 VDC or less achieve typical efficiencies exceeding 77 percent, while models with outputs of 3.3 VDC and higher reach 88 percent or more. The characteristic curves below give graphic representation of typical efficiencies achieved as a function of load at 12 VDC input.
Some advice about protection of sensitive loads
The 5080 POL converters comprise a non-isolated circuit design; there is no inherent galvanic barrier that isolates the input bus from the output side of the converter. Under some circumstances of overstress or failure originating outside the converter, the converter itself may fail short circuit, effectively coupling input to output for some duration. Therefore, the user should assess the application risk to the loads under such conditions and make provisions to implement OVP, zener clamps or voltage suppression components as may be deemed necessary. Please contact the factory for assistance.
5080 Heat Removal and Mounting Recommendations
See MDI application notes on mounting considerations for DC-DC Converters.